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general description the max5186 contains two 8-bit, simultaneous-update, current-output digital-to-analog converters (dacs) designed for superior performance in communications systems requiring analog signal reconstruction with low distortion and low-power operation. the MAX5189 pro- vides equal specifications, with on-chip precision resis- tors for voltage output operation. the max5186/ MAX5189 are designed for a 10pv-s glitch operation to minimize unwanted spurious signal components at the output. an on-board 1.2v bandgap circuit provides a well-regulated, low-noise reference that can be dis- abled for external reference operation. the max5186/MAX5189 are designed to provide a high level of signal integrity for the least amount of power dissi- pation. both dacs operate from a single supply voltage of 2.7v to 3.3v. additionally, these dacs have three modes of operation: normal, low-power standby, and complete shutdown, which provides the lowest possible power dissipation with a 1? (max) shutdown current. a fast wake-up time (0.5?) from standby mode to full dac operation allows power conservation by activating the dacs only when required. the max5186/MAX5189 are packaged in a 28-pin qsop and are specified for the extended (-40? to +85?) temperature range. for higher resolution, dual 10-bit versions, refer to the max5180/max5183 data sheet. applications signal reconstruction of i and q transmit signals digital signal processing arbitrary waveform generation (awg) imaging applications features 2.7v to 3.3v single-supply operation wide spurious-free dynamic range: 70db at f out = 2.2mhz fully differential outputs for each dac ?.5% fsr gain mismatch at f out = 2.2mhz ?.15 phase mismatch at f out = 2.2mhz low-current standby or full shutdown modes internal 1.2v, low-noise bandgap reference small 28-pin qsop package max5186/MAX5189 dual, 8-bit, 40mhz, current/voltage, simultaneous-output dacs ________________________________________________________________ maxim integrated products 1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 cref2 out2p out2n refo refr dgnd d1 dv dd d7 d6 d5 d4 d3 d2 d0 dgnd dgnd ren n.c. clk cs pd dacen av dd agnd out1n out1p cref1 qsop top view max5186 MAX5189 19-1581; rev 4; 5/03 pin configuration ordering information part max5186 beei MAX5189 beei temp range -40? to +85? -40? to +85? pin-package 28 qsop 28 qsop for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com.
max5186/MAX5189 dual, 8-bit, 40mhz, current/voltage, simultaneous-output dacs 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (av dd = dv dd = 3v, agnd = dgnd = 0, f clk = 40mhz, i fs = 1ma, 400 ? differential output, c l = 5pf, t a = t min to t max , unless otherwise noted. +25? guaranteed by production test, < +25? guaranteed by design and characterization. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd , dv dd to agnd, dgnd ................................ -0.3v to +6v digital input to dgnd.............................................. -0.3v to +6v out1p, out1n, out2p, out2n, cref1, cref2 to agnd .................................................. -0.3v to +6v ref0, refr to agnd.............................................. -0.3v to +6v agnd to dgnd................................................... -0.3v to +0.3v av dd to dv dd .................................................................... ?.3v maximum current into any pin........................................... 50ma continuous power dissipation (t a = +70?) 28-pin qsop (derate 10.8mw/? above +70?) .... 860.2mw operating temperature ranges max518_beei................................................. -40? to +85? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? gain error -4 +4 MAX5189 parameter symbol min typ max units -20 ? +20 lsb offset error -1 +1 lsb differential nonlinearity dnl -1 ?.25 +1 lsb output settling time 25 ns glitch impulse 10 pv-s sfdr 72 dbc 8 bits integral nonlinearity inl -1 ?.25 +1 lsb 57 70 dac-to-dac output isolation -60 db clock and data feedthrough 50 pv-s output noise 10 pa/ hz gain mismatch between dac outputs ?.5 ? % fsr phase mismatch between dac outputs ?.15 degrees conditions f clk = 40mhz (note 1) max5186 guaranteed monotonic to ?.5lsb error band f out = 2.2mhz all 0s to all 1s f out = 2.2mhz, t a = +25? f out = 2.2mhz resolution n spurious-free dynamic range to nyquist f out = 2.2mhz, t a = +25? f out = 550khz thd -70 dbc -68 -60 f clk = 40mhz f out = 2.2mhz, t a = +25? total harmonic distortion to nyquist f out = 550khz snr 52 db 46 52 f clk = 40mhz f out = 2.2mhz, t a = +25? signal-to-noise-ratio to nyquist f out = 550khz dynamic performance
max5186/MAX5189 dual, 8-bit, 40mhz, current/voltage, simultaneous-output dacs _______________________________________________________________________________________ 3 electrical characteristics (continued) (av dd = dv dd = 3v, agnd = dgnd = 0, f clk = 40mhz, i fs = 1ma, 400 ? differential output, c l = 5pf, t a = t min to t max , unless otherwise noted. +25? guaranteed by production test, < +25? guaranteed by design and characterization. typical values are at t a = +25?.) dac2 clk fall to data hold time t dh2 0 ns dac1 clk rise to data hold time t dh1 0 ns dac2 data to clk fall setup time t ds2 10 ns dac1 data to clk rise setup time t ds1 10 ns parameter symbol min typ max units dac external output resistor load r l 400 ? full-scale output current i fs 0.5 1 1.5 ma output leakage current -1 1 ? output voltage range v refo 1.12 1.2 1.28 v output voltage temperature drift tcv refo 50 ppm/? reference output drive capability i refo 10 ? reference supply rejection 0.5 mv/v differential full-scale output voltage v fs 400 mv voltage compliance range -0.3 0.8 v current gain (i fs /i ref ) 8 ma/ma analog power-supply voltage av dd 2.7 3.3 v analog supply current iav dd 2.7 5.0 ma digital power-supply voltage dv dd 2.7 3.3 v digital supply current idv dd 4.2 5.0 ma standby current i standby 1.0 1.5 ma shutdown current i shdn 0.5 1 ? digital input voltage high v ih 2 v digital input voltage low v il 0.8 v digital input current i in ? ? digital input capacitance c in 10 pf conditions max5186 only max5186 only dacen = 0, max5186 only pd = 0, dacen = 1, digital inputs at 0 or dv dd pd = 0, dacen = 1, digital inputs at 0 or dv dd pd = 0, dacen = 0, digital inputs at 0 or dv dd pd = 1, dacen = x, digital inputs at 0 or dv dd (x = don? care) v in = 0 or dv dd timing characteristics logic inputs and outputs power requirements analog output reference
max5186/MAX5189 dual, 8-bit, 40mhz, current/voltage, simultaneous-output dacs 4 _______________________________________________________________________________________ electrical characteristics (continued) (av dd = dv dd = 3v, agnd = dgnd = 0, f clk = 40mhz, i fs = 1ma, 400 ? differential output, c l = 5pf, t a = t min to t max , unless otherwise noted. +25? guaranteed by production test, < +25? guaranteed by design and characterization. typical values are at t a = +25?.) note 1: excludes reference and reference resistor (MAX5189) tolerance. ns 10 t cl clock low time ns 10 t ch clock high time ns 25 t clk clock period ? 50 pd fall time to v out ? 0.5 dacen rise time to v out ns 5 cs fall to clk fall time ns 5 cs fall to clk rise time parameter symbol min typ max units conditions 0.150 0.125 0.100 0.075 0.050 0.025 0 -0.025 -0.050 0 32 64 96 128 160 192 224 256 integral nonlinearity vs. digital input code max5186/9toc01 digital input code inl (lsb) 0.100 0.075 0.050 0.025 0 -0.025 -0.050 -0.075 0 32 64 96 128 160 192 224 256 differential nonlinearity vs. digital input code max5186/9toc02 digital input code dnl (lsb) 2.45 2.47 2.51 2.49 2.53 2.55 2.5 3.5 3.0 4.0 4.5 5.0 5.5 analog supply current vs. supply voltage max5186/9toc03 supply voltage (v) supply current (ma) MAX5189 max5186 1.5 2.0 3.0 2.5 3.5 4.0 -40 -15 10 35 60 85 analog supply current vs. temperature max5186/9toc04 temperature ( c) analog supply current (ma) max5186 MAX5189 0 2 6 4 8 10 2.5 3.5 3.0 4.0 4.5 5.0 5.5 digital supply current vs. supply voltage max5186/9toc05 supply voltage (v) digital supply current (ma) MAX5189 max5186 0 1 3 2 4 5 -40-1510356085 digital supply current vs. temperature max5186/9toc06 temperature ( c) digital supply current (ma) max5186 MAX5189 typical operating characteristics (av dd = dv dd = 3v, agnd = dgnd = 0, 400 ? differential output, i fs = 1ma, c l = 5pf, t a = +25?, unless otherwise noted.)
560 570 590 580 600 610 2.5 3.5 3.0 4.0 4.5 5.0 5.5 standby current vs. supply voltage max5186/9toc07 supply voltage (v) standby current ( a) MAX5189 max5186 540 560 550 580 570 590 600 -40 10 -15 356085 standby current vs. temperature max5186/9toc08 temperature (?) standby current ( a) MAX5189 max5186 0.45 0.55 0.50 0.60 0.65 0.70 0.75 0.80 2.5 3.5 3.0 4.5 4.0 5.0 5.5 shutdown current vs. supply voltage max5186/9toc09 supply voltage (v) shuitdown current ( a) max5186 MAX5189 max5186/MAX5189 dual, 8-bit, 40mhz, current/voltage, simultaneous-output dacs _______________________________________________________________________________________ 5 typical operating characteristics (continued) (av dd = dv dd = 3v, agnd = dgnd = 0, 400 ? differential output, i fs = 1ma, c l = 5pf, t a = +25?, unless otherwise noted.) 1.23 1.24 1.26 1.25 1.27 1.28 2.5 3.5 3.0 4.0 4.5 5.0 5.5 internal reference voltage vs. supply voltage max5186/9toc10 supply voltage (v) reference voltage (v) max5186 MAX5189 1.23 1.24 1.26 1.25 1.27 1.28 -40 -15 10 35 60 85 internal reference voltage vs. temperature max5186/9toc11 temperature ( c) reference voltage (v) max5186 MAX5189 0 1 2 3 4 0200 100 400 300 500 output current vs. reference current max5186/9toc12 reference current ( a) output current (ma) dynamic response rise time max5186toc13 50ns/div out_p 150mv/ div out_n 150mv/ div dynamic response fall time max5186/9toc14 50ns/div out_p 150mv/ div out_n 150mv/ div settling time max5186/9toc15 12.5ns/div out_n 100mv/ div out_p 100mv/ div
max5186/MAX5189 dual, 8-bit, 40mhz, current/voltage, simultaneous-output dacs 6 _______________________________________________________________________________________ typical operating characteristics (continued) (av dd = dv dd = 3v, agnd = dgnd = 0, 400 ? differential output, i fs = 1ma, c l = 5pf, t a = +25?, unless otherwise noted.) 40 70 60 50 80 90 100 10 30 25 15 20 35 40 45 50 55 60 max5186/9toc18 clock frequency (mhz) spurious-free dynamic range (dbc) spurious-free dynamic range vs. clock frequency dac2 dac1 fft plot, dac1 (f clk = 40mhz, 2048-point data record) f out (mhz) output power (dbm) -100 -80 -60 -40 -20 0 -120 020 16 12 8 4 f out = 2.2mhz a out = 0dbfs av dd = dv dd = 2.7v max5186/9toc16 fft plot, dac2 (f clk = 40mhz, 2048-point data record) f out (mhz) output power (dbm) -100 -80 -60 -40 -20 0 -120 020 16 12 8 4 f out = 2.2mhz a out = 0dbfs av dd = dv dd = 2.7v max5186/9toc17 60 62 64 66 68 70 72 74 0.5 0.75 1.0 1.25 1.5 spurious-free dynamic range vs. full-scale output current max5186/89-21 full-scale output current (ma) sfdr (dbc) 66 70 68 76 74 72 78 500 1100 1300 700 900 1500 1700 1900 2100 2300 max5186/9toc19 output frequency (khz) sfdr (dbc) spurious-free dynamic range vs. output frequency and clock frequency, dac1 f clk = 50mhz f clk = 60mhz f clk = 20mhz f clk = 40mhz f clk = 10mhz f clk = 30mhz 66 72 70 68 74 76 78 500 1100 1300 700 900 1500 1700 1900 2100 2300 max5186/9toc20 output frequency (khz) sfdr (dbc) spurious-free dynamic range vs. output frequency and clock frequency, dac2 f clk = 30mhz f clk = 10mhz f clk = 50mhz f clk = 60mhz f clk = 40mhz f clk = 20mhz mtpr plot (f clk = 40mhz, 4096-point data record) f out (mhz) output power (dbm) -100 -80 -60 -40 -20 0 -120 020 16 12 8 4 f t1 = 1.81mhz f t2 = 2.01mhz f t3 = 2.41mhz f t4 = 2.59mhz a out = 0dbfs av dd = dv dd = 2.7v max5186/9toc23
max5186/MAX5189 dual, 8-bit, 40mhz, current/voltage, simultaneous-output dacs _______________________________________________________________________________________ 7 pin description reference input refr 24 digital ground dgnd 23 digital supply, 2.7v to 3.3v dv dd 22 data bit d7 (msb) d7 21 7 pd power-down select 0: enter dac standby mode (dacen = dgnd) or power-up dac (dacen = dv dd ). 1: enter shutdown mode. 3 out1n negative analog output, dac1. current output for max5186; voltage output for MAX5189. data bits d1?6 d1?6 15?0 data bit d0 (lsb) d0 14 digital ground dgnd 13 digital ground dgnd 12 active-low reference enable. connect to dgnd to activate on-chip 1.2v reference. ren 11 no connect. do not connect to this pin. n.c. 10 clock input clk 9 active-low chip select cs 8 name function 1 cref1 reference bias bypass, dac1 2 out1p positive analog output, dac1. current output for max5186; voltage output for MAX5189. pin 6 dacen dac enable, digital input 0: enter dac standby mode with pd = dgnd. 1: power-up dac with pd = dgnd. x: enter shutdown mode with pd = dv dd (x = don? care). 5 av dd analog positive supply, 2.7v to 3.3v 4 agnd analog ground reference bias bypass, dac2 cref2 28 positive analog output, dac2. current output for max5186; voltage output for MAX5189. out2p 27 negative analog output, dac2. current output for max5186; voltage output for MAX5189. out2n 26 reference output refo 25
max5186/MAX5189 dual, 8-bit, 40mhz, current/voltage, simultaneous-output dacs 8 _______________________________________________________________________________________ detailed description the max5186/MAX5189 are dual, 8-bit digital-to-ana- log converters (dacs) capable of operating with clock speeds up to 40mhz. each of these dual converters consists of separate input and dac registers, followed by a current source array capable of generating up to 1.5ma full-scale output current (figure 1). an integrat- ed 1.2v voltage reference and control amplifier deter- mine the data converters?full-scale output currents/ voltages. careful reference design ensures close gain matching and excellent drift characteristics. the MAX5189? voltage output operation features matched 400 ? on-chip resistors that convert the current array current into a voltage. internal reference and control amplifier the max5186/MAX5189 provide an integrated 50ppm/?, 1.2v, low-noise bandgap reference that can be disabled and overridden by an external reference voltage. refo serves either as an external reference input or an integrated reference output. if ren is con- nected to dgnd, the internal reference is selected and refo provides a 1.2v output. due to its limited 10? output drive capability, refo must be buffered with an external amplifier if heavier loading is required. the max5186/MAX5189 also employ a control amplifier designed to simultaneously regulate the full-scale out- put current (i fs ) for both outputs of the devices. the output current is calculated as follows: i fs = 8 ? i ref where i ref is the reference output current (i ref = v refo /r set ) and i fs is the full-scale output current. r set is the reference resistor that determines the amplifier? output current on the max5186 (figure 2). this current is mirrored into the current source array where it is equally distributed between matched current segments and summed to valid output current readings for the dacs. the MAX5189 converts each output current (dac1 and dac2) into an output voltage (v out1 , v out2 ) with two internal, ground-referenced 400 ? load resistors. using the internal 1.2v reference voltage, the MAX5189? inte- grated reference output-current resistor (r set = 9.6k ? ) sets i ref to 125? and i fs to 1ma. external reference to disable the max5186/MAX5189? internal reference, connect ren to dv dd . a temperature-stable, external reference may now be applied to drive the refo pin to set the full-scale output (figure 3). choose a reference capable of supplying at least 150? to drive the bias circuit that generates the cascode current for the cur- rent array. for improved accuracy and drift perfor- mance, choose a fixed output voltage reference such as the 1.2v, 25ppm/? max6520 bandgap reference. standby mode to enter the lower power standby mode, connect digi- tal inputs pd and dacen to dgnd. in standby, both the reference and the control amplifier are active with the current array inactive. to exit this condition, dacen must be pulled high with pd held at dgnd. both the max5186/MAX5189 typically require 50? to wake up and let both outputs and reference settle. shutdown mode for lowest power consumption, the max5186/MAX5189 provide a power-down mode in which the reference, control amplifier, and current array are inactive and the dacs?supply current is reduced to 1?. to enter this mode, connect pd to dv dd . to return to active mode, connect pd to dgnd and dacen to dv dd . about 50? are required for the parts to leave shutdown mode and settle to their outputs?values prior to shutdown. table 1 lists the power-down mode selection. timing information the max5186/MAX5189 dual dacs write to their out- puts simultaneously (figure 4). on the falling edge of the clock, the input data for dac2 is preloaded into a latch. on the rising edge of the clock, input data for dac1 is loaded to the dac1 register, and the pre- loaded dac2 data in the latch is loaded to the dac2 register. outputs the max5186 outputs are designed to supply full-scale output currents of 1ma into 400 ? loads in parallel with a capacitive load of 5pf. the MAX5189 features inte- grated 400 ? resistors that restore the array currents to proportional, differential voltages of 400mv. these dif- ferential output voltages can then be used to drive a balun transformer or a low-distortion, high-speed oper- ational amplifier to convert the differential voltage into a single-ended voltage.
max5186/MAX5189 dual, 8-bit, 40mhz, current/voltage, simultaneous-output dacs _______________________________________________________________________________________ 9 applications information static and dynamic performance definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on an actual transfer function from either a best straight-line fit (closest approximation to the actual transfer curve) or a line drawn between the endpoints of the transfer func- tion, once offset and gain errors have been nullified. the max5186/MAX5189 use a straight-line endpoint fit for inl (and dnl) and the deviations are measured at every individual step. differential nonlinearity (dnl) differential nonlinearity is the difference between an actual step height and the ideal value of 1lsb. a dnl error specification no more negative than -1lsb guar- antees a monotonic transfer function. offset error the offset error is the difference between the ideal and the actual offset current/voltage. for the max5186/ MAX5189, the offset error is the midpoint value of the transfer function determined by the endpoints of a straight-line endpoint fit. this error affects all codes by the same amount. gain error gain error is the difference between the ideal and the actual output value range. this range represents the output when all digital inputs are set to 1 minus the out- put when all digital inputs are set to 0. glitch impulse a glitch is generated when a dac switches between two codes. the largest glitch is usually generated around the midscale transition, when the input pattern transitions from 011?11 to 100?00. this occurs due to timing variations between the bits. the glitch impulse is found by integrating the voltage of the glitch at the midscale transition over time. the glitch impulse is usu- ally specified in pv-s. settling time the settling time is the amount of time required from the start of a transition until the dac output settles its new output value to within the converter? specified accuracy. 9.6k ? * refr refo 1.2v ref ren current- source array dac1 switches dac2 switches 400 ? * out1p out1n out2n out2n 400 ? * 400 ? * 400 ? * msb decode clk output latches output latches input latches *internal 400 ? and 9.6k ? resistors for MAX5189 only. input latches av dd agnd cs dacen pd dv dd dgnd cref1 cref2 max5186 MAX5189 msb decode d7 d0 figure 1. functional diagram
max5186/MAX5189 dual, 8-bit, 40mhz, current/voltage, simultaneous-output dacs 10 ______________________________________________________________________________________ r set 9.6k ? i fs r set c comp * refr i ref ** refo max4040 agnd agnd dgnd 1.2v bandgap reference ren current- source array *compensation capacitor (c comp = 100nf) **9.6k ? reference current-set resistor internal to MAX5189 only. use external r set for max5186. optional external buffer for heavier loads max5186 MAX5189 i ref = v ref r set 9.6k ? * i fs 0.1 f 10 f dv dd r set refr av dd refo 1.2v bandgap reference ren current- source array external 1.2v reference *9.6k ? reference current-set resistor internal to MAX5189 only. use external r set for max5186. max5186 MAX5189 max6520 agnd agnd dgnd figure 2. setting i fs with the internal 1.2v reference and the control amplifier figure 3. max5186/MAX5189 with external reference
max5186/MAX5189 dual, 8-bit, 40mhz, current/voltage, simultaneous-output dacs ______________________________________________________________________________________ 11 figure 4. timing diagram x = don? care table 1. power-down mode selection clk input sample n - 1 for dac 1 dac 1 n - 2 n n + 1 n + 2 n + 2 n - 2 n n + 1 t ch t cl t ds1 t ds2 t clk dac 2 d0 d7 dac 1 (n - 1) dac 2 (n) dac 1 (n) dac 2 (n + 1) dac 1 (n + 1) dac 2 (n + 2) dac 1 (n + 2) dac 2 (n + 3) input sample n for dac 2 updates dac 1 and dac 2 to n updates dac 1 and dac 2 to n + 1 updates dac 1 and dac 2 to n + 2 updates dac 1 and dac 2 to n - 1 preloads sample n for dac 2 preloads sample n + 1 for dac 2 preloads sample n + 2 for dac 2 input sample n + 1 for dac 2 input sample n + 2 for dac 2 input sample n for dac 1 input sample n + 1 for dac 1 input sample n + 2 for dac 1 t dh1 t dh2 n - 1 n - 1 digital feedthrough digital feedthrough is the noise generated on a dac? output when any digital input transitions. proper board layout and grounding will significantly reduce this noise, but there will always be some feedthrough caused by the dac itself. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of the input signal? n harmonics to the fundamen- tal itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v n are the amplitudes of the 2nd- through nth-order harmonics. spurious-free dynamic range (sfdr) sfdr is the ratio of rms amplitude of the carrier frequen- cy (maximum signal component) to the rms value of the next largest noise or harmonic distortion component. sfdr is usually measured in dbc with respect to the car- rier frequency amplitude or in dbfs with respect to the dac? full-scale range. depending on its test condition, sfdr is observed within a predefined window or to nyquist. in the case of the max5186/MAX5189, the sfdr performance is measured for a 0dbfs output amplitude and analyzed within the nyquist window. thd 20 log (v v v v ) v 234 n 1 222 2 = ++ + ? ? ? ? ? ? ? ? ... ... agnd high-z agnd high-z MAX5189 max5186 shutdown x 1 last state prior to standby mode wake-up 1 0 MAX5189 max5186 standby 0 0 output state power-down mode dacen (dac enable) pd (power-down select)
max5186/MAX5189 dual, 8-bit, 40mhz, current/voltage, simultaneous-output dacs 12 ______________________________________________________________________________________ ren agnd dgnd **max5186 only out1p cref2 cref1 clk out1n out2p out2n 0.1 f 0.1 f 0.1 f dv dd av dd av dd av dd r set ** *400 ? resistors internal to MAX5189 only. max5186 MAX5189 10 f 3v 3v 0.1 f 0.1 f refr refo d0 d7 10 f 400 ? 400 ? 5v -5v 402 ? 402 ? 402 ? 402 ? * * * output 1 max4108 400 ? * 400 ? 5v -5v 402 ? 402 ? 402 ? 402 ? output 2 max4108 + + figure 5. differential to single-ended conversion using a low-distortion amplifier differential to single-ended conversion the max4108 low-distortion, high-input bandwidth amplifier may be used to generate a voltage from the array current output of the max5186. the differential voltage across out1p (or out2p) and out1n (or out2n) is converted into a single-ended voltage by designing an appropriate operational amplifier configu- ration (figure 5). i/q reconstruction in a qam application the max5186/MAX5189? low distortion supports ana- log reconstruction of in-phase (i) and quadrature (q) carrier components typically used in quadrature ampli- tude modulation (qam) architectures where i and q data are interleaved on a common data bus. a qam signal is both amplitude and phase modulated, created by summing two independently modulated carriers of identical frequency but different phase (90 phase dif- ference). in a typical qam application (figure 6), the modulation occurs in the digital domain and the max5186/ MAX5189? dual dacs may be used to reconstruct the analog i and q components. the i/q reconstruction system is completed by a quad- rature modulator that combines the reconstructed i and q components with in-phase and quadrature carrier frequencies and then sums both outputs to provide the qam signal.
max5186/MAX5189 dual, 8-bit, 40mhz, current/voltage, simultaneous-output dacs ______________________________________________________________________________________ 13 bp filter dac2 carrier frequency max2452 if q component bp filter 3v 3v digital signal processor quadrature modulator i component 0 90 3v max5186 MAX5189 dac1 figure 6. using the max5186/MAX5189 for i/q signal reconstruction grounding and power-supply decoupling grounding and power-supply decoupling strongly influ- ence the max5186/MAX5189? performance. unwanted digital crosstalk may couple through the input, refer- ence, power-supply, and ground connections, which may affect dynamic specifications like signal-to-noise ratio or sfdr. in addition, electromagnetic interference (emi) can either couple into or be generated by the max5186/MAX5189. therefore, grounding and power- supply decoupling guidelines for high-speed, high-fre- quency applications should be closely followed. first, a multilayer printed circuit (pc) board with sepa- rate ground and power-supply planes is recommend- ed. high-speed signals should be run on controlled impedance lines directly above the ground plane. since the max5186/MAX5189 have separate analog and digital ground buses (agnd and dgnd, respec- tively), the pc board should also have separate analog and digital ground sections with only one point con- necting the two. digital signals should run above the digital ground plane, and analog signals should run above the analog ground plane. digital signals should be kept far away from the sensitive analog reference and clock input. both devices have two power-supply inputs: analog v dd (av dd ) and digital v dd (dv dd ). each av dd input should be decoupled with parallel 10? and 0.1? ceramic-chip capacitors. these capacitors should be as close to the pin as possible, and their opposite ends should be as close to the ground plane as possible. the dv dd pins should also have separate 10? and 0.1? capacitors adjacent to their respective pins. try to minimize analog load capacitance for proper opera- tion. for best performance, it is recommended to bypass cref1 and cref2 with low-esr 0.1? capaci- tors to av dd . the power-supply voltages should also be decoupled with large tantalum or electrolytic capacitors at the point they enter the pc board. ferrite beads with addi- tional decoupling capacitors forming a pi network can also improve performance. chip information transistor count: 9464 substrate connected to agnd
max5186/MAX5189 dual, 8-bit, 40mhz, current/voltage, simultaneous-output dacs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. qsop.eps package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)

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